1. Field of the Invention
The present invention relates to a method of controlling a mode register set (MRS) operation in a memory device, and more particularly to a method and circuit for controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode.
2. Description of the Prior Art
Generally, a memory device is accessed in an operation mode, for example, in a state that a column address strobe (CAS) latency, a burst length, etc., are preset by a memory controller. Mode registers provide places in which set operation modes of the memory device are stored, and a series of such mode registers is called a mode register set (MRS).
FIG. 1 is a block diagram illustrating the construction of a conventional MRS control circuit.
The conventional MRS control circuit is briefly provided with an input driver 100, a first decoding means 110, a second decoding means 120 and an output driver 130.
The input driver 100 receives a mode register set command signal mrgsetup, a test mode decision address A<7> and an EMRS (Extended Mode Register Set) mode decision address BA<0>. Here, the mode register set command signal mrgsetup is a pulse signal that is enabled in a condition that signals of /CS (Chip Select), /RAS (Row Address Strobe), /CAS and /WE (Write Enable) inputted to a command decoder (not illustrated) are all in a ‘logic low’ state. The test mode decision address A<7> is an external address inputted to the 7th address pin of the memory device. Meanwhile, the EMRS mode decision address BA<0> refers to a signal for setting additional operation modes in addition to general operation modes of the memory device such as the CAS latency, burst length, etc., and particularly an EMRS operation entry signal for setting a DLL enable state, drive strength, etc.
The first decoding means 110 combines output signals of the input driver 100, and finally disables the mode register set command signal mrgsetup even in a test mode in that the test mode decision address A<7> is enabled as a ‘logic high’ state. Additionally, if the EMRS mode selection address BA<0> is enabled as a logic high state, the first decoding means 110 disables the mode register set command signal mrgsetup in the same manner as the test mode. The second decoding means 120 combines an output signal of the first decoding means 110 and a power-up signal pwrup, and if the power-up signal pwrup is enabled as a logic high state, it transfers the output signal of the first decoding means 110 to the output buffer 130. The output buffer 130 that has received the output signal of the first decoding means 110 finally outputs an address latency signal mrg_latp). Here, the power-up signal pwrup is an operation start signal that is enabled at a high level if the operation power of the memory device rises over a predetermined level.
If all the signals of /CS, /RAS, /CAS and /WE inputted to the command decoder satisfy the ‘logic low’ condition during the initial operation of the memory device, the mode register set command signal mrgsetup is enabled as a logic high state. The enabled mode register set command signal mrgsetup finally enables the address latency signal mrg_latp as a logic high state after passing through the first and second decoding means 400 and 500 together with the test mode decision address A<7> and the power-up signal pwrup.
If the address latency signal mrg_latp is enabled, the external address for setting the mode of the memory device is called from an address buffer (not illustrated), and the CAS latency, burst type, burst length, etc., of the memory device are decided during an enabled period of the mode register set command signal mrgsetup. In relation to this, an example of a mode selection table of the memory device according to the external address is illustrated in FIG. 2.
However, the conventional memory device may perform an unintended MRS operation as the mode register set command signal mrgsetup is enabled due to an internal noise component when the memory device exits from the self-refresh mode. Specifically, if the memory device exits from the self-refresh mode, all signals except for the internal power VDD return to their own potential levels from a ground level VSS. At this time, a command decoder (not illustrated) may be enabled due to a glitch because the noise component is in a state in which all the signals including the signals of /CS, /RAS, /CAS and /WE are still in a logic low state, In this case, since the signals including the signals of /CS, /RAS, /CAS and /WE inputted to the command decoder are all in the logic low state, the mode register set command signal mrgsetup inputted to the MRS control circuit is enabled to change the mode of the memory device. As described above, the MRS operation which may occur when the memory device exits from the self-refresh mode causes a malfunction of the memory device to deteriorate the performance and reliability of the memory device.